Verilator: Why Top Chip Designers Ditch Commercial Simulators

Verilator: Why Top Chip Designers Ditch Commercial Simulators

What if I told you that the most expensive line item in your chip verification budget is completely unnecessary? That the $50,000-per-seat commercial simulator your team struggles to license could be replaced with something 100 times faster—and completely free?

Here's the dirty secret Big EDA doesn't want you to know: Verilator, the open-source SystemVerilog simulator backed by the Linux Foundation and CHIPS Alliance, is quietly revolutionizing how the world's smartest semiconductor teams verify their designs. Arm uses it. RISC-V vendors ship it out-of-the-box. Over 700 contributors have battle-hardened it across billions of simulation cycles.

And yet, too many engineers still believe the myth that "open-source can't compete" in hardware verification.

They're wrong. Catastrophically wrong.

In this deep dive, I'll expose exactly why Verilator is eating commercial simulators' lunch, how its unique compilation-to-C++ architecture achieves those insane speedups, and—most importantly—how you can integrate it into your workflow today without blowing up your existing methodology. Whether you're building the next AI accelerator, verifying a RISC-V core, or simply tired of license server headaches, this is the guide that changes everything.

What Is Verilator? The Simulation Engine That Broke the Rules

Verilator is an open-source SystemVerilog simulator and lint system that takes an radically different approach to hardware simulation. Unlike traditional simulators that interpret your Verilog or SystemVerilog code at runtime, Verilator compiles your hardware description into optimized, multithreaded C++ or SystemC code. This compiled "Verilated" model then executes at native CPU speeds—no interpreter overhead, no license check latency, no artificial performance ceilings.

Created by Wilson Snyder in 2003 and now guided by the CHIPS Alliance under the Linux Foundation, Verilator has evolved from a niche academic tool into an industry powerhouse. Its dual licensing under LGPL v3 and Artistic License 2.0 means you get genuine "free as in speech and beer" flexibility—use it commercially, modify it, embed it, without the parasitic licensing costs that inflate verification budgets by 40-60%.

But why is Verilator exploding in popularity now? Three converging forces:

• The RISC-V revolution: Open ISA demands open tooling. Verilator ships with out-of-the-box support from major RISC-V IP vendors, making it the default simulation platform for the ecosystem.
• CI/CD for hardware: Modern chip development demands continuous integration. Verilator's compilation model integrates natively with software build systems (CMake, Make, Bazel), enabling hardware-in-the-loop testing that interpreted simulators simply cannot match.
• Cloud-native verification: When you're spinning up 10,000 simulation jobs on AWS^{↗ Bright Coding Blog}, per-license costs become existential. Verilator's zero-license model makes massive parallel regression economically viable.

The repository at github.com/verilator/verilator represents one of the most active open-source hardware projects in existence, with continuous benchmarking, Docker^{↗ Bright Coding Blog} distribution, and a thriving community forum.

Key Features: The Technical Arsenal That Crushes Competition

Verilator isn't just "fast for open source." It's architecturally superior to traditional approaches in ways that fundamentally change what's possible in verification.

Compilation-to-C++ Architecture

Where interpreted simulators parse and execute your HDL statement-by-statement every single cycle, Verilator performs aggressive whole-program optimization. It flattens hierarchies, inlines small modules, eliminates dead code, and applies compiler optimizations (LTO, PGO) that are impossible with runtime interpretation. The result? Your hardware becomes genuinely compiled software.

Multithreaded Simulation

Verilator automatically partitions your design across CPU threads using sophisticated dependency analysis. Single-thread performance already demolishes interpreted simulators; multithreading delivers another 2-10x speedup on modern many-core processors. Your 64-core AMD Epyc just became a hardware verification monster.

Built-in Lint and Code Quality

Before simulation even begins, Verilator performs comprehensive static analysis—catching race conditions, width mismatches, unused signals, and synthesizability issues that other tools miss until expensive debug cycles. This "shift-left" verification approach saves weeks of tapeout schedule.

SystemC Integration

Need to co-simulate with software models or legacy SystemC environments? Verilator generates standards-compliant SystemC modules that slot directly into existing virtual platforms. This hybrid modeling capability is essential for SoC verification where CPUs, GPUs, and custom accelerators must coexist.

JSON Export for Tool Chains

Verilator outputs structured JSON representations of your design's AST and hierarchy. Build custom lint rules, generate documentation, create specialized coverage tools, or feed into formal verification frameworks—your design's structure becomes programmatically accessible.

Assertion and Coverage Support

Insert SVA (SystemVerilog Assertions) and functional coverage points automatically. Verilator's coverage instrumentation integrates with standard tools like GTKWave and Surfer for visualization, creating a complete open-source verification ecosystem.

Use Cases: Where Verilator Absolutely Dominates

1. RISC-V Core Verification and Bring-Up

RISC-V's modular ISA means every implementation is slightly different. Verilator's compilation model enables cycle-accurate boot of Linux on a RISC-V core in under a minute—impossible with interpreted simulators. Vendors like SiFive and Codasip use Verilator for early software development before silicon exists.

2. AI/ML Accelerator Simulation

Modern AI accelerators feature massive parallelism—thousands of MAC units, complex memory hierarchies, and dataflow architectures. Verilator's multithreading scales simulation throughput with design parallelism, while interpreted simulators bottleneck on interpreter overhead regardless of host cores.

3. Continuous Integration Regression Suites

Imagine running your entire regression suite on every git push. Verilator's software-like build integration makes this trivial: compile once, run thousands of tests with different seeds, parallelize across CI workers. Commercial license costs would make this financially suicidal with traditional tools.

4. Virtual Platform and Software Development

Hardware isn't ready, but software must ship. Verilator-generated models run at hundreds of kHz to MHz—fast enough for meaningful software execution, accurate enough for driver development. Pair with Cocotb for Python^{↗ Bright Coding Blog}-based testbenches and you have a modern, productive verification environment.

5. Educational and Research Prototyping

Universities and research labs can't afford commercial toolchains. Verilator democratizes hardware design education, enabling students to simulate real processors and build functioning systems without licensing barriers. The CHIPS Alliance's backing ensures long-term sustainability.

Step-by-Step Installation & Setup Guide

Getting Verilator running is straightforward across platforms. Here's the complete workflow:

Prerequisites

You'll need a C++17-capable compiler, Python 3, and standard build tools:

# Ubuntu/Debian
sudo apt-get install git help2man perl python3 make autoconf g++ flex bison ccache
sudo apt-get install libgoogle-perftools-dev numactl perl-doc
sudo apt-get install libfl2  # Ubuntu only (ignore if gives error)
sudo apt-get install libfl-dev  # Ubuntu only (ignore if gives error)

# macOS with Homebrew
brew install verilator  # Or build from source below

Building from Source (Latest Features)

For bleeding-edge capabilities, compile directly from the GitHub repository:

# Clone the repository
git clone https://github.com/verilator/verilator

# Enter the directory
cd verilator

# Generate configure script (first time only)
autoconf

# Configure with optimizations and multithreading support
./configure --prefix=/usr/local

# Compile using all available cores
make -j$(nproc)

# Install system-wide
sudo make install

Docker Quick-Start (Zero Dependencies)

For immediate use without local installation:

# Pull official image
docker pull verilator/verilator:latest

# Run with your design mounted
docker run -v $(pwd):/design -w /design verilator/verilator:latest \
    verilator --binary --trace -j 0 -Wall your_design.sv

Verification Installation

Confirm successful installation:

verilator --version
# Expected: Verilator 5.0xx 2024-01-01 rev v5.0xx-xxx-gxxxxxxx

REAL Code Examples: Verilator in Action

Let's examine practical usage patterns extracted directly from Verilator's documentation and real-world workflows.

Example 1: Basic Verilation with Automatic Binary Generation

The simplest complete workflow—Verilator compiles your design and produces an executable simulator:

// counter.sv - A simple up-counter module
module counter (
    input        clk,
    input        rst_n,
    output [7:0] count
);
    reg [7:0] count_reg;
    
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            count_reg <= 8'h00;        // Synchronous reset to zero
        else
            count_reg <= count_reg + 1;  // Increment on every clock
    end
    
    assign count = count_reg;
endmodule

Compile and run with a single command:

# --binary: Generate complete simulator executable
# --trace: Enable VCD waveform generation for GTKWave viewing
# -j 0: Use all CPU cores for compilation
# -Wall: Enable all lint warnings (catches subtle bugs)
verilator --binary --trace -j 0 -Wall counter.sv

# Execute the generated simulator
./obj_dir/Vcounter

This produces Vcounter, a natively compiled executable that simulates your counter at maximum speed. The --trace flag enables VCD dump for waveform debugging—essential for understanding complex failures.

Example 2: Custom C++ Testbench with DPI Integration

For complex verification, write a C++ wrapper that instantiates the Verilated model directly:

// sim_main.cpp - Custom testbench with direct model control
#include "Vcounter.h"          // Generated by Verilator
#include "verilated.h"         // Verilator runtime
#include "verilated_vcd_c.h"   // VCD tracing support

#include <iostream>
#include <cstdlib>

int main(int argc, char** argv) {
    // Initialize Verilator's command-line parsing
    VerilatedContext* contextp = new VerilatedContext;
    contextp->commandArgs(argc, argv);
    
    // Create instance of the Verilated counter module
    Vcounter* top = new Vcounter{contextp};
    
    // Enable waveform tracing
    VerilatedVcdC* tfp = new VerilatedVcdC;
    contextp->traceEverOn(true);
    top->trace(tfp, 99);  // Trace 99 levels of hierarchy
    tfp->open("counter.vcd");
    
    // Simulation loop: 100 clock cycles
    for (int cycle = 0; cycle < 100; cycle++) {
        // Apply reset for first 5 cycles
        top->rst_n = (cycle >= 5) ? 1 : 0;
        
        // Rising clock edge
        top->clk = 1;
        top->eval();           // Evaluate combinational logic
        tfp->dump(contextp->time());  // Record waveform
        contextp->timeInc(1);  // Advance simulation time
        
        // Falling clock edge
        top->clk = 0;
        top->eval();
        tfp->dump(contextp->time());
        contextp->timeInc(1);
        
        // Print counter value after reset release
        if (cycle >= 5) {
            std::cout << "Cycle " << cycle 
                      << ": count = " << (int)top->count 
                      << std::endl;
        }
    }
    
    // Cleanup and finalization
    top->final();
    tfp->close();
    delete top;
    delete tfp;
    delete contextp;
    
    return 0;
}

Compile with Verilator's generated Makefile:

# Generate C++ with --cc (C++ mode, not --binary)
# --exe: Include our custom testbench
verilator --cc --trace --exe -j 0 -Wall counter.sv sim_main.cpp

# Build using the generated Makefile
make -C obj_dir -f Vcounter.mk Vcounter

# Run
./obj_dir/Vcounter

This pattern gives complete control over stimulus generation, result checking, and coverage collection. The eval() call triggers evaluation of all combinational logic—understanding this scheduling model is key to advanced usage.

Example 3: Multithreaded Simulation for Maximum Performance

Unlock Verilator's full potential with automatic thread partitioning:

# --threads 8: Partition design across 8 CPU threads
# --trace-threads 1: Dedicated thread for VCD writing (avoids simulation stalls)
verilator --binary --trace --threads 8 --trace-threads 1 \
    -j 0 -Wall large_design.sv

# Execute with thread affinity for consistent performance
numactl --cpunodebind=0 ./obj_dir/Vlarge_design

For designs with sufficient inherent parallelism, this achieves near-linear speedup with core count. The --trace-threads separation is crucial: without it, waveform dumping becomes a bottleneck that serializes your parallel simulation.

Example 4: Cocotb Integration for Python-Based Verification

Modern verification demands productivity. Pair Verilator with Cocotb for Python testbenches:

# test_counter.py - Python testbench using Cocotb
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer
from cocotb.result import TestFailure

@cocotb.test()
async def test_counter_increment(dut):
    """Verify counter increments correctly after reset."""
    
    # Start 100MHz clock on the dut.clk signal
    clock = Clock(dut.clk, 10, units="ns")
    cocotb.start_soon(clock.start())
    
    # Assert reset for 50ns
    dut.rst_n.value = 0
    await Timer(50, units="ns")
    dut.rst_n.value = 1
    
    # Wait for reset to propagate
    await RisingEdge(dut.clk)
    await RisingEdge(dut.clk)
    
    # Capture initial value
    initial_count = int(dut.count.value)
    
    # Check 10 increments
    for expected in range(initial_count + 1, initial_count + 11):
        await RisingEdge(dut.clk)
        actual = int(dut.count.value)
        if actual != expected:
            raise TestFailure(
                f"Count mismatch: expected {expected}, got {actual}"
            )
    
    dut._log.info("Counter increment test passed!")

Run with Cocotb's Makefile infrastructure—Verilator is a first-class supported simulator:

make SIM=verilator

This Python-based approach enables rapid test development, rich assertion libraries, and seamless integration with machine learning for coverage closure.

Advanced Usage & Best Practices: Pro Tips from Production Deployments

Compilation Time Optimization

Large designs can spend hours in Verilation. Mitigate with:

• Ccache integration: export CCACHE_CPP2=yes — caches C++ compilation
• Precompiled headers: Use --compiler-include for stable headers
• Incremental builds: Modularize design; Verilate subsystems independently

Memory Usage Control

Verilated models can consume enormous RAM for large SoCs:

# --output-split 20000: Split C++ output into 20,000-line files
# Prevents single compilation unit from exhausting compiler memory
verilator --output-split 20000 --binary large_soc.sv

Coverage-Driven Verification

Enable comprehensive coverage collection:

# --coverage: Enable line, toggle, and branch coverage
# --coverage-underscore: Include signals starting with _
verilator --binary --coverage --trace -j 0 design.sv

Merge coverage databases across regression runs and identify holes with Verilator's coverage tools or convert to industry-standard UCDB format.

Debugging Failed Verilation

When Verilator rejects valid-looking code:

# --debug: Generate internal AST dumps for understanding transformations
# --dump-tree: Output .tree files showing optimization stages
verilator --debug --dump-tree --binary problematic.sv 2>&1 | tee verilator.log

Comparison with Alternatives: The Brutal Truth

The Verdict: Choose Verilator for performance-critical digital verification, cloud-scale regression, and RISC-V/AI accelerator development. Use commercial tools only when you need analog/mixed-signal, SDF timing annotation, or complete SVA compliance for legacy IP.

FAQ: Your Burning Questions Answered

Is Verilator a complete replacement for Synopsys VCS?

Not for every use case. Verilator excels at cycle-accurate digital simulation but lacks SDF back-annotation and mixed-signal capabilities. For pure digital verification—especially software-driven testbenches—it's often superior due to speed and cost.

Can I use Verilator with existing UVM testbenches?

Partially. Verilator supports UVM 1.1d subset through third-party ports, but full UVM compliance remains work-in-progress. For new projects, consider Cocotb or native C++ testbenches as modern alternatives.

How does Verilator handle X and Z states?

Verilator uses two-state simulation (0/1) with limited X/Z handling for performance. Unknowns at startup are resolved deterministically. If your verification depends heavily on X-propagation analysis, commercial tools may be necessary—though many teams find this tradeoff acceptable.

What's the maximum design size Verilator can handle?

Millions of gates, limited primarily by host RAM. The Linux Foundation's continuous integration tests include substantial SoC designs. For extremely large designs, use --output-split and distributed compilation.

Is multithreading always beneficial?

No—small designs may slow down due to thread synchronization overhead. Benchmark with --threads 1 vs. --threads N to find your sweet spot. Designs with inherent parallelism (multiple cores, independent units) benefit most.

Can I encrypt IP for customer delivery?

Yes. Verilator supports encrypted model generation that customers can link and simulate without source access. See the commercial support options for enterprise features.

Where do I get help when stuck?

The Verilator forum and GitHub issues are actively monitored. For guaranteed response times, consider a commercial support contract.

Conclusion: The Verification Revolution Is Here—Join It

Verilator represents more than a faster simulator. It's a fundamental reimagining of how hardware verification should work in the 21st century: open, performant, cloud-native, and economically sane.

After two decades of refinement under Wilson Snyder's stewardship and the Linux Foundation's governance, Verilator has matured into a tool that outperforms commercial alternatives while eliminating their pathological licensing costs. The 700+ contributor community, Arm and RISC-V ecosystem support, and continuous benchmarking infrastructure ensure this isn't a fleeting experiment—it's infrastructure.

If you're still paying per-seat licenses for digital simulation, you're leaving performance and money on the table. If you're a student or researcher locked out of commercial tools, Verilator democratizes access to professional-grade verification. If you're building the next generation of AI chips, its multithreaded compilation model scales where interpreted simulators choke.

The future of hardware verification is compiled, open, and blazingly fast.

Clone the repository, run your first --binary compilation, and experience what 100x speedup feels like. Your regression suite—and your budget—will thank you.

👉 Get started now: github.com/verilator/verilator

👉 Read the full documentation: verilator.org/verilator_doc.html

👉 Join the community: verilator.org/forum

The license server is dead. Long live Verilator.